Logic Application Handbook: Product Features and Application InsightsNexperia UK (Ltd) - 312 pagina's This handbook is dedicated to application and design engineers who are developing and using electronic circuits, often within embedded systems for all kind of applications. The demand for discrete logic devices is widespread. Many aspects of system and board design have to be addressed and the usage of logic devices is very often generating questions and support requirements which cannot be met just by data sheets. In order to provide a compact and handy document, condensed from application notes, customer support experience and general logic knowledge, this book is meant to support development engineers who are dealing with logic devices. |
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| 17 | |
| 21 | |
| 25 | |
| 26 | |
| 32 | |
| 33 | |
| 34 | |
26 Limiting values | 35 |
62 Asynchronous Interface Logic | 93 |
622 Transceivers | 94 |
623 SchmittTriggers | 95 |
624 Voltage Translators | 96 |
625 Bidirectional translation with automatic sensing | 98 |
63 Synchronous Logic | 106 |
632 Latch or Dflipflop with level controlled enable | 107 |
633 Edge triggered flipflops and registers | 109 |
28 Static characteristics | 36 |
29 Dynamic characteristics | 38 |
Chapter 3 | 41 |
31 Static considerations | 42 |
32 Dynamic considerations | 44 |
321 Duty cycle considerations with unbalanced outputs | 46 |
323 Process family related dynamic power dissipation | 47 |
33 Power dissipation capacitance | 48 |
331 Example CPD calculations | 49 |
34 Using CPD to calculate power dissipation | 51 |
342 BiCMOS Device Calculation | 52 |
35 Results and conclusion | 53 |
Chapter 4 | 57 |
41 Synchronous and asynchronous logic | 58 |
42 Propagation delay time of a device | 59 |
43 Timing parameters of Flip Flops and Latches | 60 |
44 Skew definitions | 61 |
442 Process Skew tSKx | 62 |
46 Maximum frequency information | 64 |
Chapter 5 | 65 |
51 Application requirements for interfacing | 66 |
52 Schmitt Trigger inputs | 77 |
53 IOFF mechanism and purpose | 79 |
54 Ground and VCC bounce | 80 |
55 Bus Hold | 82 |
56 Source Termination | 84 |
Chapter 6 | 89 |
61 Analog ICs | 90 |
635 JKFlipflop | 110 |
636 ParallelRegisters | 111 |
637 FIFO Registers | 112 |
639 Monostable Multivibrator | 115 |
64 Where to use Synchronous Interface Logic | 116 |
Chapter 7 | 123 |
71 Standard Logic Packages | 124 |
72 Mini Logic Packages | 130 |
722 PicoGate Single dual or triple gate functions in small packages | 137 |
723 Leads PicoGate or no leads MicroPak? | 141 |
73 Package soldering aspects | 143 |
74 Thermal resistance of packages | 149 |
75 Thermal characterization of packages Explanation and possible setup | 153 |
Chapter 8 | 157 |
Chapter 9 | 161 |
91 The HCHCTHCU Logic Family | 165 |
92 The AHCAHCT Logic Family | 175 |
93 The LVC Logic Family | 185 |
94 The AVC Logic Family | 201 |
95 The AUP Logic Family | 212 |
96 The AXP Logic Family | 227 |
97 The LVTALVT Logic Family | 237 |
Chapter 10 | 257 |
Appendix | 269 |
Abbreviations | 299 |
| 303 | |
Legal information | 307 |
Veelvoorkomende woorden en zinsdelen
2-input action active additional analog applications Binary Buffer bus hold calculated capacitance characteristics circuit Clear clock CMOS Comparator components Conditions connected Counter datasheet diode drive Dual dynamic edge enable exact example Fairchild ON Semi Figure Flip-Flop frequency Function gate input voltage interface Inverting Latch limiting load logic devices Logic Families lower Max Unit maximum measured Multiplexer Nexperia ns Vcc open collector outputs operating output voltage packages Parameter pins power dissipation propagation delay provides Quad range recommended reset resistors result rising Schmitt trigger Schmitt-trigger Shift register shows signal single solder specified standard static Suffix supply current supply voltage switches Symbol Synchronous Table Tamb temperature three-state outputs tolerant Toshiba Transceiver transistor transition translation typical values