Principles of Verifiable RTL Design: A functional coding style supporting verification processes in VerilogSpringer Science & Business Media, 8 mei 2007 - 253 pagina's Principles of Verifiable RTL Design: A Functional Coding Style Supporting Verification Processes in Verilog explains how you can write Verilog to describe chip designs at the RT-level in a manner that cooperates with verification processes. This cooperation can return an order of magnitude improvement in performance and capacity from tools such as simulation and equivalence checkers. It reduces the labor costs of coverage and formal model checking by facilitating communication between the design engineer and the verification engineer. It also orients the RTL style to provide more useful results from the overall verification process. The intended audience for Principles of Verifiable RTL Design: A Functional Coding Style Supporting Verification Processes in Verilog is engineers and students who need an introduction to various design verification processes and a supporting functional Verilog RTL coding style. A second intended audience is engineers who have been through introductory training in Verilog and now want to develop good RTL writing practices for verification. A third audience is Verilog language instructors who are using a general text on Verilog as the course textbook but want to enrich their lectures with an emphasis on verification. A fourth audience is engineers with substantial Verilog experience who want to improve their Verilog practice to work better with RTL Verilog verification tools. A fifth audience is design consultants searching for proven verification-centric methodologies. A sixth audience is EDA verification tool implementers who want some suggestions about a minimal Verilog verification subset. Principles of Verifiable RTL Design: A Functional Coding Style Supporting Verification Processes in Verilog is based on the reality that comes from actual large-scale product design process and tool experience. |
Inhoudsopgave
| 1 | |
x | 19 |
RTL Methodology Basics 37 3 1 3 2 Simple RTL Verifiable Subset | 38 |
X Z and Other States | 67 |
RTL Formal Verification | 95 |
Formal Transformation Verification 103 5 3 1 1 5 3 1 Equivalence Checking | 103 |
Overige edities - Alles bekijken
Principles of Verifiable RTL Design: A functional coding style supporting ... Lionel Bening,Harry D. Foster Geen voorbeeld beschikbaar - 2013 |
Veelvoorkomende woorden en zinsdelen
assertion checkers assign behavior boolean bugs c_code casex Chapter clock code coverage coding style combinational logic compiler optimizations coverage metrics cycle-based simulation debugging described design errors design flow design project design verification detection EDA tool endcase endmodule equivalence checking evaluation event monitor event_trig_1 Example fanout finite state machine flip-flop formal equivalence checking formal verification functional verification gate-level simulation gates if-else ifdef implementation initial input ck instantiated keywords linting logic simulation model checking names netlist OOHD methodology optimization output port posedge ck Principle problems procedural blocks provides random regression reset RT-level RTL coding RTL model RTL simulation RTL Verilog scan sequence signal simulation compilers simulation model simulation performance statements submodule synthesis techniques testbench text macro tion tri-state two-state simulation values vectors vendor verifiable RTL design verifiable subset Verification Principle verification process verification tools Verilog language Verilog RTL VHDL wire X-state